1. Field
Embodiments of the present invention relate to etching of an integrated circuit structure. More particularly, embodiments of the present invention pertain to selective etching a metal hard mask layer used in fabricating an integrated circuit.
2. State of the Art
The fabrication of microelectronic devices involves forming electronic components on microelectronic substrates, such as silicon wafers. These electronic components may include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the electrical components to form integrated circuits. The metallization patterns are generally referred to as “interconnects.”
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, a photoresist material is patterned on a dielectric material and the dielectric material is etched through the photoresist material patterning to form a hole or a trench (hereinafter collectively referred to as “an opening” or “openings”). The photoresist material is then removed (typically by an oxygen plasma or selective wet etching) and the opening is then filled with a conductive material (e.g., such as a metal or metal alloys). The filling of the opening may be accomplished by either physical vapor deposition, chemical vapor deposition, or electroplating, as will be understood to those skilled in the art. When the opening is a hole, the resulting filled structure is referred to herein as a “via”. When the opening is a trench, the resulting filled structure is referred to herein as a “trace”. The term “interconnect” is defined herein to include all interconnection components including traces and vias.
As devices approach smaller dimensions, critical dimensions for vias and trenches become harder to achieve. Metals such as Tantalum (Ta) and Titanium (Ti) and metallic compounds such as Tantalum Nitride (TaN) and Titanium Nitride (TiN) have been used to help integrated circuit (IC) manufacturers achieve the critical dimensions for forming small vias and trenches. Metals and metallic compounds have also been used as antireflective coating and/or barrier layers in many processes to form the trenches and vias. Thus, as IC manufacturing technology enters into 0.10 um and beyond technology nodes, it is desired that metals and metallic compounds are being used as hard mark layer.
There are several known methods used to etch a metal hard mask. One method uses a high density plasma reactor in conjunction with a chlorine containing plasma. This method requires using two reactors for an IC structure having a metal hard mask layer and a dielectric layer. For the metal hard mask layer, a high density plasma reactor is used and for the dielectric layer, a medium density plasma reactor is used. The method is thus costly and complicated.
Currently, no efficient and safe composition is available for selective wet etching a metal hard mask layer. If a wet etching composition is used, it suspected to be carcinogenic, toxic, and hard to handle. More importantly, the current wet etching process typically takes a long time (e.g., about 70 minutes or more) to remove a metal hard mask layer and even so, it is not as selective to the metal as desired.
Therefore, it would be advantageous to develop a composition that can safely and efficiently etch a metal hard mask layer.